The carry operation in different fast adders are handled in a number of ways. In general, when numbers of a given length are added together, the sum may be of length greater than the individual length of each number. Consider adding two binary numbers 11+11. Addition of the right most bits (the lowest order bit position), i.e. 1+1 results in 10. While the 0 is stored in the corresponding bit position of the result, the 1 is referred to as a ‘carry’ which must be added to the sum of the bits in the next higher bit position. In this example, the 1 is added to 1+1, i.e., the sum of the digits in the next bit position, giving the final result of 110. In computer arithmetic, accounting for the carry in the next higher position is known as propagation of carry.
Various designs of fast adders could be differentiated based on their handling of the carry propagation. For example, some adders divide the bits of numbers to be added into multiple segments that are added in parallel, and then combine the sums of the segments to generate a final result. Each segment can consist of a single bit or multiple bits. The carry-select adder is an example of such an adder. In this adder, the carry from the most significant bit of one segment is propagated to the least significant bit of the next most significant segment. For example, the circuitry for adding a given segment in the carry select adder generally consists of two adders and one multiplexer. Adding two n-bit numbers with a carry select adder is done with two adders for each segment in order to perform the calculation twice, one time with the assumption of the carry being 0 and the other assuming 1. After the two results are calculated the correct sum, as well as the correct carry, are then selected with the multiplexer once the correct carry is known. This is repeated for every segment, with the correct carry result being propagated from one segment to the next. While performance can be increased by performing the two sums for each segment in parallel (e.g., dividing the time approximately by the number of segments), there may also be a cost since the addition for each segment is performed twice (e.g., a cost in area on a chip for the extra adder for each segment). Also, additional time is needed to propagate the carry result among the segments.
When adding two or more numbers of n-bits, the carry save adder outputs two n-bit numbers, one which is a sequence of partial sum bits and another which is a sequence of carry bits. For example, consider the binary sum 1101+1111. Carry-save arithmetic works by abandoning the binary notation while still working to base 2. It computes the sum digit by digit, as:
                       1101                                      +          1111                                    2212            
As seen above, the carry save adder produces a result that has to be converted back into binary and this means that carries have to propagate from right to left. The carry-save adder is typically used in adding more than two numbers, i.e. as a multi-operand adder, to justify the cost of converting the saved non-binary carries to binary, and finally adding them to the computed sum to get the final result.
In some cases a carry look ahead adder may be used to reduce the delay associated with a carry save adder. In principle the delay can be reduced so that it is proportional to log(b) where b is the number of bits in each summand, but for large numbers this is no longer the case, because even when carry look-ahead is implemented, the distances that signals have to travel on the chip increases proportionally with b, and propagation delays increase at the same rate.